基于FPGA的數(shù)字通信系統(tǒng)

電子機電論文編號:JD167    字數(shù):19521,頁數(shù):63

目錄
引言 .................................................................................5
1  數(shù)字復接系統(tǒng)簡介.................................................................. 5
2  數(shù)字復接方法及方式 ................................................................6
2.1 數(shù)字復接的方法 .................................................................. 6
2.2 數(shù)字復接的方式 .................................................................. 6
3  系統(tǒng)原理和各模塊設(shè)計 ..............................................................6
3.1 系統(tǒng)原理及框圖 .................................................................. 6
3.2 發(fā)端系統(tǒng)設(shè)計 .................................................................... 7
3.3 收端系統(tǒng)設(shè)計..................................................................... 9
3.4 FPGA的設(shè)計流程 .................................................................. 11
3.4.1 設(shè)計輸入 .................................................................. ....11
3.4.2 設(shè)計綜合 .................................................................. ....12
3.4.3 仿真驗證..................................................................  ....12
3.4.4 設(shè)計實現(xiàn) .................................................................. ....12
3.4.5 時序分析 .................................................................. ....12
3.5 發(fā)端FPGA設(shè)計 .................................................................... 13
3.5.1 分頻模塊..................................................................  ....14
3.5.2 復接模塊 .................................................................. ....15
3.5.3 顯示模塊 .................................................................. ....16
3.5.4 編譯與仿真 .................................................................... 18
3.6 收端FPGA設(shè)計 .................................................................... 19
3.6.1 數(shù)字鎖相模塊 .................................................................. 20
3.6.2 解復用模塊 .................................................................. ..21
3.6.3 顯示模塊 ...................................................................... 22
3.6.4 編譯與仿真 .................................................................. ..22
3.7 數(shù)字鎖相環(huán)原理及設(shè)計 .............................................................23
3.8 串行A/D工作原理 ..................................................................25
3.9 并行D/A的工作原理 ................................................................26
3.10 Altera Flex10K10介紹.............................................................27
4  系統(tǒng)調(diào)試 ......................................................................... 32
5  QuartusII軟件及Verilog語言簡介.....................................................32
5.1 QuartusII軟件簡介.................................................................32
5.2 Verilog語言簡介 ..................................................................34
6  結(jié)論 .................................................................. ...........35
謝辭 .................................................................. ..............36
參考文獻.................................................................. .......... 37
附  錄 .................................................................. ............38

摘  要

本設(shè)計實現(xiàn)多路數(shù)據(jù)時分復用和解復用系統(tǒng)。設(shè)計分為發(fā)端和收端，以FPGA作為主控核心。發(fā)端系統(tǒng)有三路并行數(shù)據(jù)輸入：A/D轉(zhuǎn)換數(shù)據(jù)，撥碼開關(guān)1路和撥碼開關(guān)2路。這三路數(shù)據(jù)在FPGA的控制下作為串行碼分時輸出。發(fā)端FPGA包括分頻模塊、復用模塊和電壓顯示模塊。在收端，串行數(shù)據(jù)進入FPGA，并由FPGA提取位時鐘，識別幀同步并解復用發(fā)端打包的三路碼。收端的FPGA包括數(shù)字鎖相環(huán)模塊、解復用模塊和電壓顯示模塊。發(fā)端FPGA輸入有三路8-bit數(shù)據(jù)：第一路為A/D數(shù)據(jù)、第二路和第三路是撥碼開關(guān)產(chǎn)生的數(shù)據(jù)，另外插入一路巴克碼。這四路碼組成一幀，由FPGA對其時分復用。A/D輸入端的模擬信號的電壓值通過FPGA處理，顯示在數(shù)碼管上。在收端，F(xiàn)PGA首先提取位同步，然后識別幀同步，一旦識別出幀同步，F(xiàn)PGA分別解復用三路數(shù)據(jù)。本文詳細闡述了此系統(tǒng)的設(shè)計方法，制作過程以及制作過程中的問題。設(shè)計者的工作包括：系統(tǒng)各部分電路元件的確定、確定系統(tǒng)框圖、畫出系統(tǒng)原理圖、根據(jù)原理圖設(shè)計FPGA的RTL代碼、綜合、仿真RTL代碼、設(shè)計PCB板和在線調(diào)試FPGA功能。

關(guān)鍵字：數(shù)字鎖相環(huán)；幀同步；時分復用；Verilog HDL語言；串行A/D變換；

Abstract
The system is designed for data multiplexed and de-multiplexed. It is based on TDM. The system includes the transmitter and the receiver. They are implemented mainly by FPGA. There are three inputs in the transmission system: data from A/D converter, DIP1 and DIP2. The three channels are out serially and time-divisional under the FPGA’s control. The FPGA in the transmitter is divided into four modules which are frequency divider, Barker generator, data multiplexer and voltage display. Voltage display is used for processing the data converted by ADC and sending it to the LED. The serial data are serial shifted into the FPGA in the receiver. Bit-synchronize and frame-synchronize are both picked up, and then de-multiplex.  The FPGA in the receiver is divided into three modules which are digital PLL, data de-multiplexer and voltage display. The transmitter will multiplex four ways of 8-bit parallel data. The first way is ADC data, the second and the third way is generated by dip-key. The other is Barker code used for frame synchronizing. The receiver will maintain the bit synchronizing, recognize one frame and de-multiplex three ways data. The essay will discuss the design progress, the programming idea and some problems. Works have to be done by the designer are: Specify all system components, Make system specification, Draw system schematics, Write RTL code according the schematics, Synthesis and simulate the RTL code, Design the PCBs, Validate the functions of the FPGA on-line.

Keywords: DPLL; Frame-synchronize; TDM; Verilog HDL; Serial A/D convert;