多功能頻率計的設計

電子機電論文編號:JD221    字數:23273,頁數:67       

目  錄

第1章緒論................................................................. 1
1.1  課題背景 ..............................................................1
1.2  頻率計概述.............................................................1
1.3  頻率計發展現狀 ........................................................2
1.4  FPGA概述.............................................................. 3
1.5  FPGA原理及結構.........................................................5
1.5.1  查找表（Look-Up-Table)的原理與結構...................................5
1.5.2  基于查找表（LUT)的FPGA的結構.........................................5
1.5.3  查找表結構的FPGA邏輯實現原理.........................................7
1.5.4  其他類型的FPGA和PLD .................................................7
1.6  VHDL簡介 ..............................................................8
第2章全同步頻率測量方法的研究 .............................................9
2.1  常用的數字頻率測量方法.................................................9
2.1.1  直接測頻法...........................................................9
2.1.2  多周期同步測頻方法 .................................................10
2.2  提高頻率測量精度的方案研究............................................12
2.2.1  采用對標頻信號計數的修正來提高測量精度..............................12
2.2.2  相檢式多周期同步測頻法 .............................................13
2.3  全同步數字頻率計的工作原理 ...........................................15
2.3.1  全同步頻率測量的誤差分析............................................15
2.3.2  全同步數字頻率計原理框圖 ...........................................16
第3章基于FPGA器件的功能模塊電路設計...................................... 18
3.1  脈沖同步檢測電路......................................................18
3.2  計數器............................................................... 19
3.3  鎖存器............................................................... 20
3.4  乘法器............................................................... 20
3.5  除法器 ...............................................................28
3.6  控制器 ...............................................................34
3.7  譯碼電路..............................................................36
3.8  二十進制轉換模塊......................................................36
3.9  頂層VHDL程序設計及整體仿真結果........................................39
第4章 FPGA配置方案的設計...................................................41
4.1  EPF10K30ATI144-3 FPGA芯片簡介........................................ 41
4.2  EPC2配置芯片簡介......................................................41
4.3  配置模式............................................................. 41
4.4  下載方式..............................................................42
4.5  硬件電路原理圖設計....................................................43
第5章 PCB系統板的設計 .....................................................45
結論及展望................................................................ 47
結論.............................................................. ........47
展望 ......................................................................47
參考文獻.................................................................. 50
致謝 ......................................................................51
附錄A：VHDL部分源程序 .....................................................52

摘    要
頻率是電子技術領域內的一個基本參數，同時也是一個非常重要的參數穩定的時鐘在高性能電子系統中有著舉足輕重的作用，直接決定系統性能的優劣。隨著電子技術的發展，測頻系統使用時鐘的提高,測頻技術有了相當大的發展，但不管是何種測頻方法，±1個計數誤差始終是限制測頻精度進一步提高的一個重要因素。
本設計闡述了各種數字測頻方法的優缺點。通過分析±1個計數誤差的來得出了一種新的測頻方法：檢測被測信號，時基信號的相位，當相位同步時開計數，相位再次同步時停止計數，通過相位同步來消除計數誤差，然后再通過算得到實際頻率的大小。根據M/T法的測頻原理，已經出現了等精度的測頻方法但是還存在±1的計數誤差。因此，本文根據等精度測頻原理中閘門時間只與測信號同步，而不與標準信號同步的缺點，通過分析已有等精度測頻方法所存±1個計數誤差的來源，采用了全同步的測頻原理在FPGA器件上實現了全同步字頻率計。根據全同步數字頻率計的測頻原理方框圖，采用VHDL語言，成功編寫出了設計程序，并在MAX+PLUSⅡ軟件環境中，對編寫的VHDL程序進了仿真，得到了很好的效果。最后，又討論了全同步頻率計的硬件設計并給出了電路原理圖和PCB圖。對構成全同步數字頻率計的每一個模塊，給出了較詳細設計方法和完整的程序設計以及仿真結果。
關鍵詞：FPGA、頻率計、VHDL語言、MAX+PLUSⅡ
Abstract
Frequency is a basic parameter of electronics field,meanwhile,it’s a very important parameter.Stable clock is very important in high performance electronics system,determining the syetem performance directly.With the development of technology of electronics,the frequency measurement system using higher clock,the frequency measurement technology has very nice development.In despite of using all other advanced frequency measurement methods,the positive and negative 1 errors was a very important factor that stop frequency measurement precision improving all through.
The design expound the advantage and disadvantage of most digital frequency measurement methods.Through analyzing the origin of the positive and negative 1 errors,got a new frequency measurement methods:checking the measured and standard signal’s phase,if the phase is synchronous,then the counters start counting,when the signal’s phase is synchronous again,the counter stopping working,by phase in-phase to eliminate counting errors,then getting the real frequency through calculating.By this way’s guide,the design of complete digital cymometer was successfully completed with using VHDL(Very High Speed Integrated Circuit Hard Design Language）hardware description language and simulated it right.According to all of Synchronous Digital Block diagram of the frequency measurement using VHDL,the successful preparation of the design process,and in MAX+PLUS II software environment,the preparation of procedures for VHDL simulation,obtained very good results.Lastly,the frequency synchronization of the whole discussion of the hardware design and gives the circuit schematics and PCB plans.All of a synchronous digital frequency of each module,is a more detailed design and integrity of the process design and simulation results.
Keyword：FPGA、Cymometer、VHDL、MAXPLUSⅡ