集成運放參數測試儀

電子論文編號:JD1103  論文字數:8375,頁數:31

目 錄
第一章 方案比較設計與論證 5
1.1測量電路模塊 5
1.1.1測試信號源部分 5
1.1.2主測試電路 5
1.1.3信號放大電路 6
1.1.4濾波電路 6
1.2信號采集模塊 7
1.3用戶接口模塊 7
1.3.1 顯示方案: 7
1.3.2 鍵盤輸入方案: 7
第二章 整機工作原理與功能實現 8
第三章 各子模塊的設計 12
第四章 理論計算及分析 18
第五章 電路圖及有關設計文件 23
第六章 系統測試 27
參考文獻： 30
第七章 結論 31

摘要：本系統參照片上系統的設計架構、采用FPGA與SPCE061A相結合的方法，以SPCE061A單片機為進程控制和任務調度核心；FPGA做為外圍擴展，內部自建系統總線，地址譯碼采用全譯碼方式。FPGA內部建有DDS控制器，單片機通過系統總線向規定的存儲單元中送入正弦表；然后DDS控制器以設定的頻率，自動循環掃描，生成高精度，高穩定的5Hz基準測量信號。掃頻信號通過對30MHz的FPGA系統時鐘進行分頻和外部鎖相環（FPGA采用FLEX10K10無內部鎖相環）倍頻，產生高頻率穩定度、幅值穩定度的掃頻信號。放大器參數測量參照GB3442-82標準，低頻信號幅度的測量采取AD高速采樣，然后進行數字處理的方法；高頻信號的幅度直接采用集成有效值轉換芯片測得。A/D轉換采用SPCE061A內部自帶的10位AD。SPCE061A主要實現用戶接口界面（鍵盤掃描、液晶顯示、數據打印以及其他服務進程的調度）、AD轉換以及測量參數（Vio Iio Kcmr Avd BWG Tr）計算、與上位機通信等方面的功能。上位機主要實現向下位機發送測量指令、與下位機交換測量數據、以及數據的存儲、回放、統計。
 
關鍵詞： 參數測量 運算放大器 DDS FPGA SPCE061A 數字信號處理
Abstract: In light of this system on-chip system design architecture, using a combination of FPGA and SPCE061A ways to SPCE061A SCM process control and task scheduling for the core; FPGA as an external expansion, internal self-built system bus, the address decoding all-Decoding. FPGA internal built DDS controller, microcontroller through the system bus to the provisions of the storage unit into the sine table; then DDS controller to set the frequency, auto-loop scanning, generating high-precision, high stability, 5Hz baseline measurement signal. Sweep the signal through the FPGA system clock 30MHz sub-band and the external phase-locked loop (FPGA using FLEX10K10 not have an internal phase-locked loop) frequency doubling, resulting in a high frequency stability, amplitude stability of the sweep signal. Amplifier parameter measurement reference GB3442-82 standard, low-frequency signal amplitude measurements taken by AD high-speed sampling, and then digital processing methods; high-frequency signals using an integrated RMS magnitude of the direct conversion chip measured. A / D converter uses the internal SPCE061A native 10-bit AD. Main achieved SPCE061A User Interface (Keyboard scanning, LCD display, data printing and other services to the process of scheduling), AD conversion, and measured parameters (Vio Iio Kcmr Avd BWG Tr) calculated with the host computer communication, etc. functions. Host machine is mainly send the measure to achieve the down-bit machine instructions, and the next crew exchange of measurement data, and data storage, playback, statistics.

Key words: parameter measurement op-amp DDS FPGA SPCE061A digital signal processing