電子測頻儀--畢業(yè)設(shè)計

電子機(jī)電論文編號:JD025    字?jǐn)?shù):15138,頁數(shù):56

目  錄
摘    要................................................................... i
目    錄..................................................................  ii
第1章 緒    論 ............................................................ 1
第2章電子測頻儀的設(shè)計原理................................................  5
2.1 電子測頻儀的基本組成 .................................................. 5
2.2 電子測頻儀的分類........................................................6
2.4電子測頻儀的基本工作原理...............................................  6
2.5電子測頻儀技術(shù)指標(biāo)及誤差分析...........................................  8
第3章   CPLD簡介 ......................................................... .10
3.1 CPLD器件結(jié)構(gòu)簡介....................................................... 10
3.2典型CPLD器件簡述 ....................................................... 12
3.3 CPLD的編程工藝..........................................................14
3.4新技術(shù)的應(yīng)用 ............................................................15
第4章電子測頻儀設(shè)計環(huán)境簡介...................................  ...........17
4.1 Quartus Ⅱ開發(fā)軟件簡介 .................................................17
4.1.1 圖形用戶界面設(shè)計流程 .......................................... ......18
4.1.2 EDA工具設(shè)計流程 ..................................................... 18
4.1.3 Quartus Ⅱ軟件的主要設(shè)計特性..........................................18
第5章電子測頻儀的設(shè)計 .............................................. ......21
5.1 電子測頻儀設(shè)計任務(wù)及要求................................................21
5.2 設(shè)計實(shí)現(xiàn) .............................................................. 21
5.3 功能模塊設(shè)計 ...........................................................23
5.4 下面分別介紹各模塊基于VHDL的設(shè)計方法................................... 23
5.5 頂層文件的編寫........................................................  41
5.6程序說明 ............................................................... 44
5.7系統(tǒng)仿真 ............................................................... 44
第6章  結(jié)    論 ........................................................... 46
致    謝 .................................................................. 47
參 考 文獻(xiàn) ............................................................... 48

摘  要
    電子測頻儀是一種基本的測量儀器，是用數(shù)字顯示被測信號頻率的儀器，被測信號可以是正弦波，方波或其它周期性變化的信號。因此，它被廣泛應(yīng)用與航天、電子、測控等領(lǐng)域。它的基本測量原理是，首先讓被測信號與標(biāo)準(zhǔn)信號一起通過一個閘門，然后用計數(shù)器計數(shù)信號脈沖的個數(shù)，把標(biāo)準(zhǔn)時間內(nèi)的計數(shù)的結(jié)果，用鎖存器鎖存起來，最后用顯示譯碼器，把鎖存的結(jié)果用LED數(shù)碼顯示管顯示出來。根據(jù)數(shù)字頻率計的基本原理，本文設(shè)計方案的基本思想是分為五個模塊來實(shí)現(xiàn)其功能，即整個數(shù)字頻率計系統(tǒng)分為分頻模塊、防抖電路、計數(shù)模塊、鎖存器模塊和顯示模塊等幾個單元，并且分別用VHDL對其進(jìn)行編程，實(shí)現(xiàn)了閘門控制信號、計數(shù)電路、鎖存電路、位選電路、段選電路、顯示電路等。本文詳細(xì)論述了利用VHDL硬件描述語言設(shè)計，并在EDA（電子設(shè)計自動化）工具的幫助下，用大規(guī)模可編程器件（CPLD）實(shí)現(xiàn)數(shù)字頻率計的設(shè)計原理及相關(guān)程序。該設(shè)計方案對其中部分元件進(jìn)行編程，實(shí)現(xiàn)了閘門控制信號、多路選擇電路、計數(shù)電路、位選電路、段選電路等。頻率計的測頻范圍：10KHz~9.9MHz。該設(shè)計方案通過了Max+plus Ⅱ軟件仿真、硬件調(diào)試和軟硬件綜合測試。

關(guān)鍵詞：數(shù)字頻率計  電子設(shè)計自動化 大規(guī)模可編程器件 硬件描述語言

Abstract

The electronic frequency measurement meter is one kind of basic metering equipment, is with the digit demonstrated that was measured the signaling frequency the instrument, was measured the signal may be the sine wave, the square-wave or other periodic variation signal. Therefore, it is widely applied and domains and so on astronautics, electron, observation. Its preliminary survey principle is, first lets measure that the signal and the standard signal through a strobe, then with the counter counting signal pulse's integer, standard time's in counting's result, save together with the latch lock, finally uses to demonstrate the decoder, saves the result the lock to demonstrate with the LED numerical code display tube. According to the digital frequency meter's basic principle, this article design proposal's basic philosophy is divides into five modules to realize its function, namely the entire digital frequency meter system divides into the frequency division module, against to shake the electric circuit, the counting module, the latch module and the display module and so on several units, and uses VHDL to carry on the programming separately to it, realized the strobe control signal, the counting circuit, the lock to save the electric circuit, the position to choose the electric circuit, the section to choose the electric circuit, the display circuit and so on. This article elaborated in detail has used the VHDL hardware description language design, and in EDA (electronic design automation) under tool's help, (CPLD) realized the digital frequency meter's principle of design and the dependent program with the large-scale programmable component. This design proposal to the partial parts carries on the programming, realized the strobe control signal, the multi-channel selecting circuits, the counting circuit, the position to choose the electric circuit, the section to choose the electric circuit and so on. Frequency meter's frequency measurement scope: 10KHz~9.9MHz. This design proposal passed Max+plus ⅡSoftware simulation, hardware debug and software and hardware line-up test.

key word: Digital frequency meter electron design automation large-scale programmable component hardware description language