基于VHDL數字頻率計的設計與仿真

電子機電論文編號:JD133  字數:8993,頁數:36

目 錄
摘要 .....................................................................I
Abstract .................................................................Ⅱ
1 EDA、VHDL簡介............................................................1
1.1 EDA技術................................................................1
1.2 硬件描述語言——VHDL ..................................................1
1.2.1 VHDL的簡介.......................................................... 1
1.2.2 VHDL語言的特點 ......................................................2
1.2.3 VHDL的設計流程 ......................................................2
2.數字頻率計的設計方案與功能實現 ..........................................4
2.1 數字頻率計的基本原理...................................................4
2.2 數字頻率計各模塊的設計.................................................4
2.2.1 分頻模塊.............................................................5
2.2.2 主控模塊 ............................................................6
2.2.3 寄存器模塊.......................................................... 9
2.2.4 七段譯碼模塊 .......................................................11
2.2.5 動態掃描模塊 .......................................................12
2.2.6 數據選擇器模塊......................................................13
2.2.7 五進制計數分頻模塊 .................................................14
2.2.8 數字頻率計總的原理圖 ...............................................15
3 系統仿真 ...............................................................17
3.1 分頻器模塊仿真 .......................................................17
3.2 主控模塊仿真..........................................................17
3.3 寄存器模塊仿真 .......................................................19
3.4 七段譯碼顯示模塊仿真 .................................................19
3.5 數據選擇器模塊的仿真 .................................................20
3.6 動態掃描模塊的仿真 ...................................................20
3.7 數字頻率計總系統仿真 .................................................21
4 硬件仿真................................................................23
總結 .....................................................................24
致謝.....................................................................25
參考文獻 .................................................................26
附錄 .....................................................................27

摘 要
VHDL（Very High Speed Integrated Circuit Hardware Description Language,超高速集成電路硬件描述語言）誕生于1982年，是由美國國防部開發的一種快速設計電路的工具，目前已經成為IEEE（The Institute of Electrical and Electronics Engineers）的一種工業標準硬件描述語言。相比傳統的電路系統的設計方法，VHDL具有多層次描述系統硬件功能的能力，支持自頂向下（Top to Down）和基于庫（LibraryBased）的設計的特點。
本數字頻率計是一種以VHDL（硬件描述性語言）為基礎采用自頂而下設計方法實現的。該設計要能測量方波信號頻率的頻率計，測量結果用4位十進制數表示，頻率測量范圍分為四檔，并用數碼顯示管顯示其頻率；同時設置了一個量程狀態顯示信號，在超出最大量程時報警。

關鍵字：VHDL語言,數字頻率計, EDA技術，QUARTUSⅡ

Abstract
VHDL (Very High Speed Integrated Circuit Hardware Description Language, high-speed integrated circuit HDL) was born in 1982, is from the U.S. Department of Defense developed a fast circuit design tools, has now become the IEEE (The Institute of Electrical and Electronics Engineers) an industry-standard hardware description language. Compared to the traditional system of circuit design, VHDL description of a multi-level system hardware features the ability to support top-down (Top to Down) and based on the (LibraryBased) the design characteristics.
This is a digital frequency of the VHDL (hardware description language) based on a top-down design methods to realize. The design must be able to measure the frequency square-wave frequency of measurement results with four decimal number, frequency range is divided into Sidang and digital display shows the frequency at the same time set up a status display signal range in excess of the largest Alarm at the range.

Keywords: VHDL language,Digital frequency meter, EDA technology, QUARTUSⅡ