低頻數(shù)字式相位差測量儀的設(shè)計

電子機(jī)電論文編號:JD706  論文字?jǐn)?shù):21132,頁數(shù):78

目錄
序言 …………………………………………………………………………………1
系統(tǒng)方案設(shè)計……………………………………………………………….2
設(shè)計任務(wù)的分析………………………………………………………………2
1.1.1設(shè)計主要內(nèi)容及基本要求…………………………………………………. 2
1.1.2設(shè)計研究主要條件及技術(shù)指標(biāo) ………………………………………….2
1.2系統(tǒng)方案的選擇………………………………………………………………. 2
1.3 系統(tǒng)的總體設(shè)計方案…………………………………………………………… 3
第二章 系統(tǒng)硬件電路的設(shè)計……………………………………………………… .4
2.1 信號整形電路的設(shè)計……………………………………………………………4
2.1.1 LM339 的簡介………………………………………………………………4
2.1.2最簡單的信號整形電路的設(shè)計……………………………………………4
2.1.3采用了施密特觸發(fā)器組成的信號整形電路的設(shè)計 ……………………..5
2.2 FPGA數(shù)據(jù)采集電路 ……………………………………………………………6
2.2.1 FPGA數(shù)據(jù)采集電路的功能分析……………………………………………6
2.2.2 FPGA數(shù)據(jù)采集電路的原理 ……………………………………………….7
2.2.3 FPGA數(shù)據(jù)采集電路中各模塊確定…………………………………………8
2.3單片機(jī)數(shù)據(jù)運(yùn)算控制電路的設(shè)計……………………………………………….9
2.3.1單片機(jī)數(shù)據(jù)運(yùn)算控制電路的設(shè)計………………………………………..9
2.3.2數(shù)據(jù)顯示電路的設(shè)計 ……………………………………………………10
第三章 軟件部分的設(shè)計……………………………………………………………14
3.1 FPGA數(shù)據(jù)采集電路的VHDL語言程序設(shè)計…………………………………14
3.1.1 VHDL語言的簡介…………………………………………………………14
3.1.2 VHDL語言程序設(shè)計………………………………………………………14
3.2單片機(jī)數(shù)據(jù)運(yùn)算控制電路的程序設(shè)計…………………………………………15
3.2.1 數(shù)據(jù)處理的技巧分析 …………………………………………………….15
3.2.2 軟件設(shè)計思路………………………………………………………………15
第四章 系統(tǒng)的制作與調(diào)試…………………………………………………………20
4.1硬件電路的制作與調(diào)試………………………………………………………20
4.1.1硬件電路的制作………………………………………………………….20
4.1.2硬件電路的調(diào)試………………………………………………………….20
4.2軟件系統(tǒng)的調(diào)試 ……………………………………………………………….21
4.2.1 FPGA數(shù)據(jù)采集電路的調(diào)試……………………………………………….21
4.2.2單片機(jī)數(shù)據(jù)運(yùn)算控制電路的軟件制作與調(diào)試…………………………..25
4.3系統(tǒng)的聯(lián)合調(diào)試與驗證…………………………………………………………26
結(jié)束語 ……………………………………………………………………………27
參考文獻(xiàn)………………………………………………………………………….28
附錄一 元器件清單 ………………………………………………………….30
附錄二 程序清單……………………………………………………………….31
1.單片機(jī)源程序…………………………………………………………….31
2.VHDL語言源程序 ……………………………………………………….47
3.測顯示用的匯編程序……………………………………………………54
附錄三 實物圖……………………………………………………………………56
附錄四 英文翻譯 ………………………………………………………………58

摘要:本設(shè)計——低頻數(shù)字式相位差測量系統(tǒng)使用FPGA和單片機(jī)相結(jié)合，構(gòu)成整個系統(tǒng)的測控主體。FPGA主要負(fù)責(zé)采集兩個同頻待測正弦信號的頻率和相位差所對應(yīng)的時間差，而兩個同頻待測正弦信號經(jīng)過信號整形電路變成方波后送入FPGA數(shù)據(jù)采集電路中。而單片機(jī)負(fù)責(zé)讀取FPGA所采集到的數(shù)據(jù)并根據(jù)這些數(shù)據(jù)計算待測正弦信號的頻率和相位差，并同時通過功能鍵切換在八位七段共陽極數(shù)碼管上顯示出待測信號的頻率和相位差,具有數(shù)字顯示功能。此系統(tǒng)具有不易受外界干擾，可靠性好，測量精度高等優(yōu)點(diǎn)。如在此設(shè)計基礎(chǔ)上進(jìn)一步從可靠性、穩(wěn)定性等方面進(jìn)行完善，便可應(yīng)用于實際的工業(yè)系統(tǒng)之中。

關(guān)鍵詞：相位差；測量；FPGA；單片機(jī)

The Design of Low-Frequency Digital Phase Difference Measurement Instrument

Abstract: The design that low-frequency digital phase difference measurement system combines FPGA with SCM which constitutes the main measuring and controlling system of this entire design. FPGA is used to collect the time differences respectively corresponding to the frequency and phase difference of the measured sine signals with the same frequency .Ahead of that ，the measured sine signals of the same frequency should be changed to the forms of square waves by the plastic circuit module.At the same time, SCM is used to accept the data signals collected by FPGA , and then according to these data signals ,calculates the frequency and phase difference of the measured sine signals with the same frequency. And also on the meanwhile, SCM can switch the function buttons to show frequency and phase difference by the 8 Common Anode Seven-Segment LEDs which have the functions of digital display. This system can resist the outside interferences and has the advantages of reliability and high- precision measurement .If this design is further improved in stabilization and reliability , it can be used in the real industrial system .

Keywords: phase difference; measurement; FPGA; SCM