基于EDA的計(jì)算器的設(shè)計(jì)

電子機(jī)電論文編號(hào):JD854 附開題報(bào)告,任務(wù)書,外文翻譯,論文字?jǐn)?shù):16873,頁數(shù):42

摘要 Ⅰ
目次  Ⅲ
術(shù)語表 Ⅳ
1 引言 1
1.1 EDA技術(shù) 1
1.1.1 EDA技術(shù)的涵義 1
1.1.2 EDA技術(shù)的發(fā)展歷程 1
1.1.3 EDA的技術(shù)的基本特征和基本工具 1
1.2 VHDL語言 2
1.2.1 VHDL語言的特點(diǎn) 2
1.2.2 VHDL語言設(shè)計(jì)實(shí)體的基本結(jié)構(gòu) 3
1.2.3 VHDL語言的實(shí)體 3
1.2.4 VHDL語言的結(jié)構(gòu)體 3
1.2.5 VHDL程序設(shè)計(jì)約定 4
2 設(shè)計(jì)規(guī)劃 5
2.1 基于EDA的計(jì)算器的功能 5
2.2 計(jì)算器的設(shè)計(jì)思路 5
2.2.1 計(jì)算器的計(jì)算部分 5
2.2.2 計(jì)算器的存儲(chǔ)部分 5
2.2.3 計(jì)算器的顯示部分 6
2.2.4 計(jì)算器的輸入部分 6
2.3 系統(tǒng)組成框圖 6
3 計(jì)算器各模塊的設(shè)計(jì)和實(shí)現(xiàn) 7
3.1 基于EDA的計(jì)算器計(jì)算部分的設(shè)計(jì)和實(shí)現(xiàn) 7
3.1.1 加法器的設(shè)計(jì) 7
3.1.2 減法器的設(shè)計(jì) 10
3.1.3 乘法器的設(shè)計(jì) 12
3.1.4 除法器的設(shè)計(jì) 13
3.2 計(jì)算器計(jì)算器輸入部分的設(shè)計(jì)和實(shí)現(xiàn) 17
3.3 計(jì)算器顯示部分的設(shè)計(jì)和實(shí)現(xiàn) 20
3.4 8位二進(jìn)制數(shù)轉(zhuǎn)換成個(gè)位、十位、百位的模塊 21
4 計(jì)算器的綜合設(shè)計(jì) 25
4.1 整體的程序設(shè)計(jì) 25
4.2 計(jì)算器的仿真波形 26
5 結(jié)論 32
參考文獻(xiàn) 33
致謝 34
附錄 35

摘要：EDA是指利用計(jì)算機(jī)完成電子系統(tǒng)的設(shè)計(jì)。在基于EDA的計(jì)算器的設(shè)計(jì)中，主要研究了的是8位二進(jìn)制數(shù)的加減法運(yùn)算、兩個(gè)4位二進(jìn)制數(shù)的乘法運(yùn)算、8位二進(jìn)制數(shù)除以4位二進(jìn)制數(shù)的除法運(yùn)算以及連續(xù)的加減運(yùn)算的實(shí)現(xiàn)方法。本系統(tǒng)選用Altera公司的MAX+PluseⅡ作為硬件開發(fā)平臺(tái),并采用VHDL語言進(jìn)行電路設(shè)計(jì)。在設(shè)計(jì)的過程中采用的是分模塊的設(shè)計(jì)方法，將計(jì)算器分為四個(gè)部分：計(jì)算部分、存儲(chǔ)部分、顯示部分和輸入部分。計(jì)算部分主要有加法器、減法器、乘法器和除法器組成。存儲(chǔ)部分需要3個(gè)存儲(chǔ)器來實(shí)現(xiàn)：內(nèi)部累加器（acc）、輸入寄存器（reg）以及結(jié)果暫存器（ans）。顯示部分由三個(gè)7段譯碼器組成，分別來顯示輸入數(shù)字。輸入部分是由0——9十個(gè)數(shù)字按鍵、加減乘除四則運(yùn)算的運(yùn)算符按鍵、一個(gè)等號(hào)按鍵和一個(gè)清零按鍵組成的，設(shè)計(jì)所要做的是對(duì)按鍵信息進(jìn)行譯碼（將十進(jìn)制數(shù)轉(zhuǎn)換成為二進(jìn)制數(shù)），使其在計(jì)算器內(nèi)部可以使用。

關(guān)鍵詞：EDA；計(jì)算器；VHDL

The Calculator Based on EDA Design

Abstract：EDA is the used of the computer to complete the design of electronic systems. The calculator based on EDA design, it main studies the 8-bit binary number of addition and subtraction operations, the two 4-bit binary number multiplication, 8-bit binary number divided by the number of four binary division, as well as implementation for continuous operation of addition and subtraction operations. The system selected Altera's MAX + Pluse Ⅱ as a hardware development platform, and the use of VHDL design languages. In the design process is used frequency division modules, the calculator is divided into four parts: calculate, storage, display and input part. The calculate is composed of four parts：addertion, subtraction, and multiplier and divider components. Storage part needs three memory to help achieved: internal accumulator (acc), input register (reg) as well as the results of registers (ans). Display part is made up three decoder of 7 sections, respectively to show the number of input. Input part has ten number keys, from 0 – 9, also has addition and subtraction and multiplication and division arithmetic operator keys, a button and of equal sign and the clear key, the design has to decode the key information (to be decimal digital conversion as a binary number), so that you can use these in the internal of calculator.

Key words： EDA；calclute；VHDL