Digital communication, digital transmission, video transmission, computer network, such as digital signal conversion and transmission encountered in the most important issue is the question of reliability. In this design we have adopted as a FIFO shift register, through the VHDL hardware design language frequency, so that we can read and write operation have been different rates of change. In this design, we have adopted maxplux2 simulation environment, called related chip to form a complete circuit..Therefore, - a simple and reliable code transform circuit speed digital information transmission system is essential.
Through the Shannon coding theorem for the study: each channel has a channel capacity to determine the Cp, as long as no more than Rs transmission rate Cp, there is a code on a certain way, with the introduction of maximum-likelihood decoding, the bit error rate Re arbitrary small. Shannon theorem we to understand the process of encoding information.
This paper introduces the CPLD design of the code rate conversion circuit based on FIFO, resulting in the definition and related functions. Introduced through the FPGA in a flexible environment muxplux memory design. Through the FIFO, VHDL language to achieve the realization of sub-frequency rate of change of control memory devices.
Keywords: Code transform circuit speed, Rate of transformation, FIFO.
