四路分接器的設(shè)計

通信工程論文編號:TX326  論文字數(shù):15196,頁數(shù):31

目錄

摘要 I
ABSTRACT II
第1章 引言 1
 1.1  課題設(shè)計的歷史及發(fā)展前景 1
 1.2  研究內(nèi)容 2
第2章 開發(fā)平臺及語言介紹 3
 2.1 MAX＋PLUS II介紹 3
 2.2 FPGA介紹 5
 2.3 VHDL介紹 6
第3章 四路分接器 8
 3.1 數(shù)字分接器原理框圖 8
 3.2 位同步時鐘信號的提取 9
 3.3 幀同步信號的提取 10
 3.4 時序信號恢復(fù) 10
 3.5分路器模塊 10
第4章 四路分接器的建模 12
 4.1系統(tǒng)功能要求 12
 4.2 四路同步分接器的功能框圖模型 13
第5章 同步分接器的設(shè)計 14
 5.1各部分功能模塊的原理圖 14
 5.1.1 32位輸出的串/并變換電路模塊 14
 5.1.2 時序信號恢復(fù)模塊 15
 5.1.3 分路器模塊的原理圖 18
 5.1.4 串/并、并/串變換器模塊的原理圖 20
 5.2頂層原理圖的建立 22
 5.2.1時序仿真 23
 5.3 設(shè)計中遇到的問題 23
第6章 結(jié)束語 25
致謝 26
參考文獻 27

摘要
 數(shù)字復(fù)接技術(shù)是數(shù)字通信網(wǎng)的一門基礎(chǔ)技術(shù)。它發(fā)展到20世紀80年代已經(jīng)趨于成熟，它不僅是與信源編碼、數(shù)字傳輸、數(shù)字交換相并列的專門技術(shù)，而且還是網(wǎng)同步中的幀調(diào)整，線路集中器中的線路復(fù)用及數(shù)字交換中的時分接續(xù)等技術(shù)的基礎(chǔ)。一個數(shù)字復(fù)接系統(tǒng)由數(shù)字復(fù)接器、數(shù)字分接器和傳輸信道共同構(gòu)成。
 本文提出了基于FPGA技術(shù)實現(xiàn)數(shù)字復(fù)接系統(tǒng)的設(shè)計中有代表性的較簡單的四路同步分接器系統(tǒng)總體設(shè)計。數(shù)字分接器的作用主要是將數(shù)字復(fù)接器復(fù)接后經(jīng)過傳輸?shù)牡竭_接收端口的信號進行解復(fù)接的操作，將信號還原。這次設(shè)計Max+plusII軟件來進行仿真設(shè)計。相對VHDL文本的輸入方法，本設(shè)計采用了原理圖輸入法來完成設(shè)計，提高設(shè)計的效率。
 迄今為止，很少用FPGA來實現(xiàn)復(fù)接器專用芯片的設(shè)計，所以本次設(shè)計有它的設(shè)計意義與研究價值。
 
關(guān)鍵詞： 四路分接器，VHDL， Max+plusII
 ABSTRACT

 Digital multiplexing technology is a digital communications network based on a technology. When the 80's years of the 20th century it have become more mature, and it is not only the technical expertise along with a source coding, digital transmission, digital switching, but also the division basis of the use in the frame synchronization network adjustment, line concentrator reuse of lines and digital switching follow-up of technologies such as time. A digital multiplexer is made up with the digital multiplexer system, the digital distribution and the transmission channel .     In this paper, it’s a digital multiplexer system based on FPGA technology to achieve a system of the four-way synchronization system design Demultiplexer which is design simpler and more representative . The mainly useful of Digital Demultiplexer will be that the signal ,which had been multiplexered by the digital multiplexer and after it transmission through the signals channel and reach the receiving , access the operation of demultiplexing, the signal will be reduction. The design used the Max + plusII design simulation software . Relative VHDL text input method, experimental schematic used to complete the design input to improve the efficiency of the design.     To date, people unusually use FPGA to achieve the Digital multiplexing technology design, so the design of the significance have its design and research value.

Keywords: Digital Demultiplexer , VHDL, Max+plusII