關鍵詞：確定性測試，全掃描測試，掃描鏈阻塞，旅行商問題，低功耗測試
A Low Power Deterministic Test Using Scan Chain Disable Technique Based on a TSP Approach
Abstract
Due to the chip density increasing drastically through the last decade, power dissipation becomes one of the most important factors of very large scale integration design. Furthermore, power and energy consumption of digital systems are considerably higher in test mode than in normal mode. In particular, in the case of scan test, the power dissipation due to clocking all the scan flip-flops is so excessive that it may burn the chip .Hence, many techniques have investigated power minimization or power constrains test.
Test power dissipation depends directly on the global clock frequency and switching transitions of the circuit under test. Therefore, decreasing both the clock frequency and the switching activity can reduce test power. Scan chain disable technique can reduce test power efficiently. In the technique, the flip-flops are grouped into N scan chains. At sometime, just one scan chain or some of the scan chains are active. Average power is reduced. We previously proposed a low power deterministic test methodology. In this method, only a scan chain is active during both shift and capture cycles. Both peak power and average power are reduced drastically. However, the test application time of some benchmark circuits is increased. We find that if we reorder the test set, the test application time can be reduced. The problem to achieve shortest test application time is equivalent to a TSP problem. Experimental results show that our approach can efficiently reduce test application time.
