A Low Cost Test for Extended Compatibilities Scan Tree Architecture ABSTRACT
With the transistor counts exponentially increasing, scan-based designs are widely employed to reduce test generation time. Full scan-based design is one of the most important designs for testability (DFT) methodologies in very large scale integration (VLSI) circuits and in system-on-chip (SoC) cores. In this DFT methodology, all flip-flops are enhanced to scan cells, and test application time depends on the length of the longest scan chain. Though full scan design reduces test generation complexity drastically, the test cost including test application time, test data volume and test power is very high, and it increases the cost of automatic test equipment (ATE).
Recently, scan tree techniques have been proposed to reduce test application time. In these techniques, scan cells are constructed into a tree structure. The length of the longest scan chain is reduced. During scan operation, test data are shifted into the scan tree via one scan cell at the root. The scan cells in the same level have the same shifted test data. Therefore, to keep fault coverage, the scan cells should be compatible for all the test vectors. We previously proposed an extended compatibilities scan tree technique, employing logic NOT and XOR functions, reduces test application time and average test power drastically by shifting the same test values into(out from) the compatible scan flip-flops simultaneously. However, the hardware overhead is higher. In particular, the number of scan outputs is too larger so that the compact of test response data is difficult.
This thesis proposes a scan tree architecture of extended compatibilities based on the concept of dumb element. This method can efficiently reduce the number of scan outputs. Experimental results show that our approach achieves almost the same test application time, test input data volume, test power and area overhead compared with the previous construction. For S38584 of ISCAS’89 benchmark circuits, the test response data volume reduces 48.3%.
Keywords：design for testability, full scan testing, scan tree, low power testing
