基于FPGA的FIR濾波器設(shè)計

電子通信論文編號:TX192  論文字數(shù):29262,頁數(shù):73

目  錄

1 引言……………………………………………………………… 5
2 基于乘累加結(jié)構(gòu)的FIR數(shù)字濾波器…………………………… 6 
3 基于對稱并行結(jié)構(gòu)的流水線算法……………………………… 7
3.1 實現(xiàn)FIR濾波器的三種方案………………………………… 7
   3.1.1 分布式算法……………………………………………………7
3.1.2 串行方式………………………………………………………… 7
3.1.3 并行方式………………………………………………………… 7
3.2 FIR濾波器的具體實現(xiàn)……………………………………… 8
3.2.1 表達式的直接優(yōu)化……………………………………………… 8
3.2.2 加法樹乘法器結(jié)構(gòu)……………………………………………… 8
3.2.3 流水線優(yōu)化技術(shù)………………………………………………… 11
3.2.4 總體結(jié)構(gòu)………………………………………………………… 11
4 Matlab設(shè)計FIR濾波器………………………………………… 13
4.1 傳統(tǒng)設(shè)計方法………………………………………………… 13
4.2 MATLAB設(shè)計方法………………………………………………13
4.2.1 FDATool簡介…………………………………………………… 13
4.2.2  設(shè)計流程………………………………………………………… 14
5 硬件電路設(shè)計…………………………………………………… 17
5.1 系統(tǒng)框圖……………………………………………………… 17
5.2 FPGA最小系統(tǒng)……………………………………………… 17
5.3 外圍電路設(shè)計………………………………………………… 20
5.3.1 信號調(diào)理電路………………………………………………… 20
5.3.2 AD轉(zhuǎn)換電路…………………………………………………… 24
5.3.3 DA轉(zhuǎn)換電路…………………………………………………… 25
5.3.4 音頻放大電路………………………………………………… 26
6 軟件設(shè)計…………………………………………………………  28
6.1 開發(fā)軟件和編程語言………………………………………… 28
6.2 開發(fā)流程……………………………………………………… 28
6.3 主程序流程圖………………………………………………… 29
6.4 仿真結(jié)果……………………………………………………… 31
6.4.1 串并轉(zhuǎn)換……………………………………………………… 31
6.4.2 分頻器………………………………………………………… 31
6.4.3 AD轉(zhuǎn)換………………………………………………………… 32
6.4.4 加法樹乘法器………………………………………………… 33
6.4.5 FIR濾波器…………………………………………………… 33
6.4.6 并串轉(zhuǎn)換……………………………………………………… 35
6.4.7 DA轉(zhuǎn)換………………………………………………………… 36
6.4.8 按鍵檢測……………………………………………………… 37
7 結(jié)束語…………………………………………………………… 39
致謝………………………………………………………………… 40
參考文獻…………………………………………………………… 41
附錄………………………………………………………………… 42
附錄1 部分中英文對照………………………………………… 42
附錄2  源代碼清單……………………………………………… 43
附錄3 英文原文………………………………………………… 55
附錄4 中文譯文………………………………………………… 65

摘要：數(shù)字濾波是語音和圖象處理、模式識別、譜分析等應(yīng)用中的一個基本處理算法,在數(shù)字信號處理中, 它占有極其重要的地位. 針對常用的軟、硬件方法實現(xiàn)語音FIR濾波器存在的問題，文章提出了一種在MATLAB的FDA界面上設(shè)計FIR數(shù)字濾波器的新方法和采用現(xiàn)場可編程門陣列器件FPGA并行高速實現(xiàn)語音濾波的硬件解決方案，并以一個16階低通FIR數(shù)字濾波器的實現(xiàn)為例說明利用Altera公司Cyclone系列芯片的設(shè)計過程。這種方案可以方便地調(diào)整濾波器的階數(shù)和系數(shù)，適合不同場合的應(yīng)用。文章提出的對稱并行流水結(jié)構(gòu)可以同時兼顧FPGA綜合的速度和面積，實現(xiàn)了FIR濾波器的硬件優(yōu)化設(shè)計。與其他類型的濾波器相比，這種結(jié)構(gòu)類型的濾波器在資源耗用、濾波速度和功耗等方面表現(xiàn)出更優(yōu)異的性能。仿真表明，在系數(shù)量化數(shù)據(jù)寬度為16位時，系統(tǒng)在高達130MHz時鐘頻率下能夠穩(wěn)定可靠地工作，可以滿足一些高精度實時處理系統(tǒng)對精度和速度的要求。

關(guān)鍵字：FIR  FPGA  線性相位  并行流水 

Design of FIR Filter Running on FPGA
Abstract: Digital filter is a basic settlement calculation method to speech sounds,image settlement,pattern discrimination and chart analysis.It plays a very important role in digital signal processing.Aiming at the problems in designing the audio FIR filter using software and hardware,a scheme is proposed which designs a FIR filter by the FDATool based on the MATLAB and runs it on FPGA parallelly with high speed.The article introduces the design process of  a 16 order low-pass FIR digital filter using a Cyclone-chip provided by Altera company.The orders and coefficients of the filter may flexibly be adjusted to apply it in various applications.The connection between synthesis area restriction and speed restriction can be flexibly optimized through this improved FIR filter architecture arithmetic,which is symmetric, parallel and using pipelining technology.Compared with other FIR filters,this type performs better including resources sharing、processing speed and power absorption.Through programming and simulating,it is shown that the system can work stably at the 130MHz frequency when the bits of coefficient quantization come to 16 ,proving the scheme is effective for designing high speed and real-time digital filter.

Keywords: FIR    FPGA   linear phase   parallel and pipelining