QPSK調制與解調模塊

電子通信論文編號:TX205 附原理圖及PCB,程序,論文字數:20215,頁數:39

以下為一級目錄,詳細目錄及內容請與本站聯系

目    錄

引言………………………………………………………………………1
1 設計方案 ……………………………………………………………１
2 鎖相環頻率合成設計…………………………………………………2
3 調制解調模塊設計…………………………………………………19
4  序列信號發生電路…………………………………………………30
5  電源設計……………………………………………………………31
6　軟件設計…………………………………………………………32
7　測試方法和改進……………………………………………………35
8　結論………………………………………………………………37
謝辭……………………………………………………………………38
參考文獻………………………………………………………………39

摘   要

四相相移鍵控信號簡稱“QPSK”,這種調制方式由于抗干擾能力強、頻帶利用率高等特點，得到廣泛的應用，比如微波、衛星通信系統、寬帶接入與移動通信等，現成為現代通信中的一種十分重要的調制解調方式。
瑣相環路是一個能夠跟蹤輸入信號相位的閉環自動控制系統，它廣泛應用于廣播通信、頻率合成、自動控制及時鐘同步等技術領域。鎖相環主要由相位比較器（PC）、壓控振蕩器（VCO）、低通濾波器(LP)三部分組成。PLL具有載波跟蹤特性；調制跟蹤特性；高精度的相位和頻率測量；用高穩定的參考振蕩器鎖定，可作提供一系列頻率高穩定的頻率源等特點，現已出現了各種數字鎖相環路，在數字信號傳輸方面起到了重要作用。
本課題的設計任務是實現QPSK的調制與解調，頻率范圍為35MHz-70MHz。在本設計中著重介紹了QPSK的調制、解調原理以及實現調制解調所需要的載波的具體實現方法：根據鎖相環路可提供高穩定的頻率源，在設計中采用鎖相頻率合成得到穩定的調制解調所需的載波；采用數字集成正交調制解調芯片實現QPSK的調制與解調。在論文中詳細闡述了相位調制的調制解調原理、瑣相環頻率合成的原理以及分別的實現的電路設計和調試方法。

關鍵字：四相相移鍵控；鎖相環；頻率合成；調制；解調

 Abstract

 Quaternary Phase Shift Keying is short for QPSK, this modulation method  gets an extensive application,because its anti-interference ability is superior to many others,and the wave band is taken good advantage of,an so on.It is used
in many domains ,such as microwave and Satellite communication system ,theconnect into the wideband,Mobile communication system. nowadays QPSK has become a more important way of modulation and demodulation in modem co-mmunication system .
The phase locking loop (PLL ) is a automatic control system that can foll-ow closing the phase of the input signal .It applies to technological fields , s-uch as broadcast communication , frequency formating ,Automaticallying controland clock synchronization ,etc. extensively.the phase locking cycle is made up of three part:Phase Distinction (PD),Voltage-Controlled Oscillator (VCO ),Lowpass Filter (LP ).the PLL has the character of tracking carrier and modulation ,and it can be used to measure the phase and frequency precisely,and whena high stable standard scillator is set to be locked,it can supply a series of high stabl-e frequency.now many kind of digital PLL,it play a important roles in the tra-nsmission of digital signal .
  This  design assignment is to realize the modulation and demodulation of  QPSK in the frequency range from 35MHz to 70MHz.in this thesis ,it emphas-izes  on the method access to the QPSK modulation and demodulation ,and h-ow to get the carrier that the modulation and demodulation needed.I use a mo-nolithic IC of quadrature modulator and demodulator to realize the QPSK mod-ulation and demodulation.according to the PLL’s character of supplying high st-able frequency signals,in this design,we get the stable carrier by the Phaselock-ed Frequency Multiplier.in the following words,you can see the details of the  principle of modulation,demodulation and the the Phase-locked Frequency Mult-iplier,and the methods of ectronic circuit design for the three.

Keywords: Quaternary Phase Shift Keying(QPSK);PLL; modulation; dem-odulation; Phase-locked Frequency Multiplier